This disclosure relates generally to analysis of network packets and, more specifically, to analysis of network packets using a generated hash code.
A typical network packet includes a packet header that has a defined number of bytes. Analysis of a packet header has typically been required in order to assign a network packet to an appropriate packet flow (i.e., an appropriate receive or transmit queue). As analysis of an entire packet header may be time consuming, hash codes (which are usually short compared to entire packet headers) of packet headers have been utilized to reduce analysis time. Reducing the time required to identify a packet flow is even more desirable when multiple packet headers (i.e., a packet header of a lower layer network packet and a packet header of an upper layer network packet) have to be analyzed to identify a packet flow. In general, hash codes may have different lengths depending on processing requirements and, as such, flexibility in calculating hash functions is usually desirable. The usability of a hash code depends on the entropy of the generated hash code. In general, hash codes with higher entropy have higher information content and, as such, more accurately identify a packet flow of a network packet.
The flexibility of hash functions have typically been defined by two parameters: the way in which the hash key is assembled; and the properties of the hash function. Several trade-offs are often made to implement flexible hashers by playing on variations of the two properties. In general, flexibility in hash key assembly may be better achieved in software implementations of hashers, while flexible hash functions usually involve some form of configurable hardware hasher implementation. Each aspect of hasher flexibility typically comes with limitations. For example, software key assemblies have performance limitations when complex patterns are required to build the hash key (in particular, when the key assembly is done at bit-level granularity). As another example, configurable hardware hash functions have silicon area limitations due to the configuration logic implementing the base hashing elements, which are typically implemented with exclusive OR (XOR) gates. The limitations appear to be especially significant when a hasher is used for identifying packet flows on very high-speed interfaces (e.g., 10 Gbps or more), mainly due to very short packet periodicity (e.g., 67.2 ns or less).